NES hardware (NESdev Wiki)

The APU has two pulse channels, each with four duty settings, 12.5%, 25%, 50%, and 25% negated (75%), as 8-step sequences. nes-hardware/pulse-duty

About: Music driver

Value

{
 "channels": 2,
 "duty": [
  0.125,
  0.25,
  0.5,
  0.75
 ],
 "sequences": [
  "01000000",
  "01100000",
  "01111000",
  "10011111"
 ]
}

WikiAPU Pulse · leadEach of the two NES APU pulse (square) wave channels generate a pulse wave with variable duty.APU Pulse · Sequencer behavior1 0 0 1 1 1 1 1 (25% negated)Checked by claude, 2026-10-21 — read the duty table in the pinned capture

Cited by: Music driver

A pulse channel's frequency is $f = f_{C P U} / (16 (t + 1))$ for an 11-bit timer period $t$ , with $f_{C P U}$ = 1.789773 MHz on NTSC; periods below 8 silence the channel. nes-hardware/pulse-frequency

About: Music driver

Value

{
 "cpuHz": 1789773,
 "divisor": 16,
 "minPeriod": 8
}

WikiAPU Pulse · Pulse channel output to mixerfpulse = fCPU/(16*(t+1)) (where fCPU is 1.789773 MHz for NTSCAPU Pulse · Pulse channel output to mixerA period of t < 8, either set explicitly or via a sweep period update, silences the corresponding pulse channel.Checked by claude, 2026-10-21 — read the pinned capture

Cited by: Music driver

The triangle channel steps a fixed 32-step sequence, 15 down to 0 and back up, at $f = f_{C P U} / (32 (t + 1))$ , so it has no duty or volume setting. nes-hardware/triangle

About: Music driver

Value

{
 "steps": 32,
 "divisor": 32
}

WikiAPU Triangle · leadThe sequencer sends the following looping 32-step sequence of values to the mixer:APU Triangle · leadf = fCPU ÷ (32 × (tval + 1))APU Triangle · leadThe triangle channel contains the following: timer, length counter, linear counter, linear counter reload flag, control flag, sequencer.Checked by claude, 2026-10-21 — read the pinned capture

The page lists no volume or envelope unit among the triangle's parts; a program can only gate it with the linear and length counters.

Cited by: Music driver

The noise channel clocks a 15-bit shift register at one of 16 periods; in normal mode the sequence is 32,767 steps long, and the periodic mode gives 93- or 31-step loops. nes-hardware/noise

About: Music driver

Value

{
 "periodsNTSC": [
  4,
  8,
  16,
  32,
  64,
  96,
  128,
  160,
  202,
  254,
  380,
  508,
  762,
  1016,
  2034,
  4068
 ],
 "normalSteps": 32767,
 "periodicSteps": [
  93,
  31
 ]
}

WikiAPU Noise · Noise mode and period ($400E, write)The period determines how many CPU cycles happen between shift register clocks.APU Noise · OperationThis results in a pseudo-random bit sequence, 32767 steps long when Mode flag is clear, and randomly 93 or 31 steps long otherwise.Checked by claude, 2026-10-21 — read the NTSC column of the period table in the pinned capture

Cited by: Music driver

The delta modulation channel (DMC) plays 1-bit delta-encoded samples from $$ C 000 + 64 A$ , $16 L + 1$ bytes long, at one of 16 rates; a program can also load its 7-bit output level directly through $4011. nes-hardware/dmc

About: DPCM samples

Value

{
 "ratesNTSC": [
  428,
  380,
  340,
  320,
  286,
  254,
  226,
  214,
  190,
  160,
  142,
  128,
  106,
  84,
  72,
  54
 ],
 "address": "$C000 + 64A",
 "length": "16L + 1"
}

WikiAPU DMC · leadThe NES APU's delta modulation channel (DMC) can output 1-bit delta-encoded samples or can have its 7-bit counter directly loaded, allowing flexible manual sample playback.APU DMC · OverviewSample address = %11AAAAAA.AA000000 = $C000 + (A * 64)APU DMC · OverviewSample length = %LLLL.LLLL0001 = (L * 16) + 1 bytesAPU DMC · Pitch tableFor example, on NTSC (1.789773 MHz), a rate of 428 gives a frequency of 1789773/428 Hz = 4181.71 Hz.Checked by claude, 2026-10-21 — read the NTSC rate row and the address and length formulas in the pinned capture

At NTSC, rate $F (54 cycles) is 33,144 Hz, $E (72) is 24,858 Hz, and $D (84) is 21,307 Hz.

Cited by: DPCM samples, Music driver, Sampled sound

The PPU's object attribute memory (OAM) holds a display list of up to 64 sprites, 4 bytes each, and sprite 0 is the one at OAM bytes $00-$03. nes-hardware/oam

About: Sprite flicker

Value: 64 sprites

WikiPPU OAM · leadcontains a display list of up to 64 sprites, where each sprite's information occupies 4 bytes.PPU OAM · Sprite 0 hitsSprite 0 is the sprite controlled by OAM addresses $00-$03Checked by claude, 2026-10-21 — read the pinned capture

Cited by: Sprite flicker

On each scanline the PPU copies the sprites in range, searching OAM in order, into a secondary OAM that holds 8, so a scanline shows at most 8 sprites and the later ones in OAM order drop out. nes-hardware/sprites-per-scanline

About: Sprite flicker

Value: 8 sprites per scanline

WikiPPU OAM · Internal operationthe PPU contains 32 bytes (enough for 8 sprites) of secondary OAM memoryPPU OAM · Internal operationa linear search of the entire primary OAM is carried out to find sprites that are within y range for the next scanlineChecked by claude, 2026-10-21 — read the pinned capture

Cited by: Sprite flicker

A sprite 0 hit happens when an opaque pixel of sprite 0 overlaps an opaque background pixel; it sets bit 6 of PPUSTATUS ($2002), which stays set until the pre-render line, so a frame reports only its first hit. nes-hardware/sprite-0-hit

About: Status bar split

Value

{
 "register": "$2002",
 "bit": 6
}

WikiPPU OAM · Sprite 0 hitsWhile the PPU is drawing the picture, when an opaque pixel of sprite 0 overlaps an opaque pixel of the background, this is a sprite 0 hit.PPU OAM · Sprite 0 hitsBit 6 of PPUSTATUS ($2002) is cleared to 0 at dot 1 of the pre-render line. This means only the first sprite 0 hit in a frame can be detected.Checked by claude, 2026-10-21 — read the pinned capture

Cited by: Status bar split

A nametable is 1,024 bytes, 32 by 30 tiles of 8 by 8 pixels plus a 64-byte attribute table, and the PPU addresses four logical nametables in a 2 by 2 grid from $2000. nes-hardware/nametables

About: Raster effects

Value

{
 "columns": 32,
 "rows": 30,
 "bytes": 1024,
 "attributeBytes": 64,
 "bases": [
  "$2000",
  "$2400",
  "$2800",
  "$2C00"
 ]
}

WikiPPU nametables · leadeach nametable has 30 rows of 32 tiles each, for 960 ($3C0) bytes; the 64 ($40) remaining bytes are used by each nametable's attribute table.PPU nametables · MirroringThe NES has four logical nametables, arranged in a 2x2 pattern.Checked by claude, 2026-10-21 — read the pinned capture

Without a split, a program sets the background's position once per frame by writing X and Y to $2005 and the coordinates' high bits to $2000; a split changes the scroll position while the frame is drawn, for instance by writing $2006 twice. nes-hardware/scroll

About: Raster effects

WikiPPU scrolling · Frequent pitfallsIf the screen does not use split-scrolling, setting the position of the background requires only writing the X and Y coordinates to $2005 and the high bit of both coordinates to $2000.PPU scrolling · Split X/Y scrollBy writing twice to $2006, the second write causes an immediate full reload of v from t, allowing you to update the vertical scroll in the middle of the screen.Checked by claude, 2026-10-21 — read the pinned capture

Cited by: Raster effects

Backgrounds and sprites each have 4 palettes of 4 entries at $3F00-$3F1F; entry 0 of each is transparent, and entry 0 of palette 0 is the backdrop shared by both, so each palette shows 3 colors of its own. nes-hardware/palettes

About: Palette cycling

Value

{
 "backgroundPalettes": 4,
 "spritePalettes": 4,
 "colorsEach": 3,
 "backdrop": "$3F00",
 "colors": 64
}

WikiPPU palettes · Palette RAMBackgrounds and sprites each have 4 palettes of 4 colors, located at $3F00-$3F1F in VRAM.PPU palettes · Palette RAMEntry 0 of each palette is unique in that it is transparent, so its color value is normally unused.PPU palettes · Palette RAMThe backdrop color is the single color shown behind both the background and sprites, wherever both layers are transparent.Checked by claude, 2026-10-21 — read the pinned capture

Cited by: Palette cycling

The MMC3 mapper counts scanlines by watching the PPU's address line A12, reloads its counter from a latch at zero, and raises an IRQ when the counter reaches zero with IRQs enabled. nes-hardware/mmc3-irq

About: Status bar split

WikiMMC3 · IRQ SpecificsThe MMC3 scanline counter is based entirely on PPU A12MMC3 · IRQ SpecificsWhen the IRQ is clocked (filtered A12 0→1), the counter value is checked - if zero or the reload flag is true, it's reloaded with the IRQ latched value at $C000; otherwise, it decrements.MMC3 · IRQ SpecificsIf the IRQ counter is zero and IRQs are enabled ($E001), an IRQ is triggered.Checked by claude, 2026-10-21 — read the pinned capture

Cited by: Status bar split

The MMC3 maps the PPU's 8 KB of pattern space as two switchable 2 KB banks and four switchable 1 KB banks, each selected by a register write. nes-hardware/mmc3-chr-banks

About: CHR bank switching

Value

{
 "banks2KB": 2,
 "banks1KB": 4
}

WikiMMC3 · CHR BanksPPU $0800-$0FFF (or $1800-$1FFF): 2 KB switchable CHR bankMMC3 · CHR BanksPPU $1C00-$1FFF (or $0C00-$0FFF): 1 KB switchable CHR bankChecked by claude, 2026-10-21 — read the CHR bank list in the pinned capture

Cited by: CHR bank switching